Shift Register Realizations of Asynchronous Sequential Machines

Unitary Shift-Register Realizations of Sequential Machines

Definite Asynchronous Sequential Circuits

An asynchronous unit delay is an n input n output of the input n-tuple prior to the last inlput change. It asynchronous sequential circuit in which the present value of the will then be shown that every asynchronous definite flow output n-tuple is equal to the value of the input n-tuple prior to the last input change. This paper considers the problem of determining ablecan brizeday a fee bac r ...

On Shift Register Realization of Sequential Circuits II

This is the second of a series of intended reports on realization of sequential machines with shift registers and on properties of shift registers. Some of the pathological cases for the shift register realization algorithms SRR/GSRR reported in the previous report are investigated here. One of the pathological cases turned out to be simple cycles, and based on the work of Yoeli, an algorithm h...

On Shift Register Realization of Sequential Circuits

Realizing a sequential machine with shift registers is an attractive approach to the design for testability. It requires little extra circuit for scan and since feed-backs are always to the rst ip-op of a shift register test generation is expected to be easier than that for circuits with unstructured feedbacks. Though the shift register realization of sequential machines was studied by several ...

On the Use of Redundancy in Successive Approximation A/d Converters

In practical realizations of sequential (or pipelined) A/D converters, some form of redundancy is typically employed to help absorb imperfections in the underlying circuits. The purpose of this paper is to review the various ways in which redundancy has been used in successive approximating register (SAR) ADCs, and to connect findings from the information theory community to ideas that drive mo...